Column Contents
Device
ND-K003H uPD78002x,uPD78003x
ND-K007H uPD78007x
ND-K01H uPD7801x
ND-K0148H 78K0Kx1series
ND-K030H uPD7805x,uPD7806x,uPD78005x,uPD78030x
ND-K033H uPD78031x,uPD78032x,uPD78033x
ND-K04H uPD7804x
ND-K08H uPD7807x,uPD7808x
Emulation Emulation Frequency Equal to the subject device (except for the device applied to high-speed )
Emulation Clock Input-able to Internal/External clock of the internal In circuit emulator
Emulation Memory Program: 64 Kbytes
Emulation Mapping IROM  4KB
IRAM  128B
Extended memory 8KB
Event Detection Detenction Bus Detection Element IROM  4KB
IRAM  128B
Extended memory 8KB
Detenction Address 0h~FFFFh
Area Able (limited for BRS1, BRS2 )
Mask Able
Data Byte,Bit mask: Able
Status R/W/RW
Detenction Program Detection Element 2 detectors
Detenction Address 0h~FFFFh
Mask Able
Parallel Point 7 points (only for BRS1)
Sequential Point 4 points (only for BRS1)
Extra Data 1bit
Event Integration Qualify Execute Qualify trace (BRA only) by event detect result
Trace Delay Start Trace delay by event detect result
Trigger Same as delay event (MAX:1)
Break Event Break Break by event detect result
Step Break Break by Step completed
Manual Break Break by Stop key, etc.
Failsafe SFR Access to non-existing SFR area
Data Memory Access to non-existing data memory area
Stack Overflow of stack
IMS Register For the debugger setting, If the set size of IMS register is bigger than the internal ROM size.
Trace Trace Capacity 8K
Trace Data Address/Data Total 40bits
Trace Condition All trace
Qualify trace
Trace Delay Switch by L/M/F
Time Test From Run execution to Break (Resolution 62.5ns)
Data Sampler Data indication in real time
Low Voltage 2V~5V
Host I/F Exclusive parallel interface
Run Reset function (CPU Reset and System Reset: Able)
Real time execution, Break execution, Step execution
Status indicate function (For during RUN, Trace, Standby)
other Control Soft Windows applied
Other Able to Change Memory/Register/SPR in Break
Window close