Column			Contents
Device			ND-K403H ： uPD78403x ND-K404H ： uPD78404x, uPD784054 ND-K422H ： uPD78422x, uPD78421xA
Emulation	Emulation Frequency		Same as the subject device
	Emulation Clock		Input-able to Internal/External clock of the internal In circuit emulator
	Emulation Extra Memory		The sharing of the same memory for Internal ROM
	Emulation Internal Memory		Internal RAM: same as the real chip (512B) Peripheral RAM: same as the real chip (MAX: 32KB) Internal ROM: 192KB (Extended memory NE-105 mounted)
	Emulation Extra Mapping		64KB space or more: By 4KB 1MB space or less: By 64KB 1MB space or more: 1MB
	Emulation Kind of Mapping		Alternative ROM, Alternative RAM, User memory, Guard memory
Event Detection	Detenction Bus	Detection Element	4 detectors
		Detenction Address	0h～FFFFFh
		Mask	Able
		Data	Byte,Bit mask: Able
		Status	BR/OP/R/W/RW/RM/WM/RWM/RP/WP/RWP/VECT/NC
	Detenction Program	Detection Element	4 detectors
		Detenction Address	1bit
		Mask	Able
	Extra Data		1bit
	Detection Bus		Specify 1 detector from the event detect result, and count the numbers of event occurrence. 8bit counter×1
	Sequential		Specify 4 detectors from the event detect result, and operate the sequence.Step: 4 steps, function: 1, Disable condition: not specified
	Qualify		Execute Qualify trace (BRA only) by the event detect result
	Trace Start		Start trace by the event detect result and path, sequential condition detect.
	Trace End		Stop trace by the event detect result and path, sequential condition detect.
	Trace Delay		Start trace delay by the event detect result.
	Trigger		Same as the delay event.
Break	Event Break		Break by the event detect result and path, sequential condition detect.
	Step Break		Break by the step execution completed.
	Manual Break		Break by the command.
	Failsafe	SFR	Non-map SFR, Writing to R/O SFR, Read from W/R, Different access unit
		Light Protect	Write to Internal ROM, alternative ROM
		Guard	Program execution/Access of Card area
		Relocation	Access to different area of the relocation
Trace	Trace Capacity		32K step
	Trace Data		Internal/External Bus Total 96bits
	Trace Condition		All trace Qualify trace Section trace
	Trace Delay		Settable 0-32K frame
Time Test	Start		Same as Section trace start event
	Stop		Same as Section trace stop event
	Resolution		203.45ns
	Max Time		14 mins. 33 secs.
	Functions		32bit ×1
	Quantity Survey		Max　65536times
	Average		Provided
RAM Realtime			Internal high-speed RAM area
Low Voltage			3V～
Host I/F			Exclusive Bus interface
Run			Reset function (CPU Reset and System Reset: Able) Real time execution, Break execution, Step execution Status indicate function (LED indicates READY/HOLD, the status during RUN, Trace, Standby are indicated on the screen)
other	Mask		HLDRQ signal can be masked by Hardware MNI signal can be masked by Hardware WAIT signal can be masked by Hardware RESET signal can be masked by Software HARDWARE STOP signal can be masked by Software
	Control Soft		Windows applied
	Other		Able to Change Memory/Register/SPR in Break

※Trace memory board NT-323 in use

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